Advances in semiconductor technology are placing demands on higher level system packaging. Monolithic integrated circuit technology has been a driving force behind electronics growth. It is therefore logical to look to integrated circuit techniques for system level packaging.
While substantial innovations have been made in packaging semiconductor components and devices, there is a need for more efficient and economical packaging techniques. Miniaturization and thermal dissipation characteristics of presently available packaging are not fully adequate to take advantage of inherent performance characteristics of current devices.
With the emergence of very large scale integrated (VLSI) circuits, it becomes necessary for system integration development to package such circuits together so as not to compromise the advancements in circuit integration. VLSI circuits, such as one megabit random access memory circuits, are packaged in a plastic or ceramic encapsulant and are available in either as a dual in-line package, or as a leadless chip carrier. Both of these approaches address the packaging problems of single integrated circuit chips, but do not present solutions to system integrated and/or packaging of multiple chips.
Hybrid wafer packaging technology has been used to flip-chip mount semiconductor chips on substrates or by vertically mounting the semiconductor chips on the substrate. The signal and power terminals of the semiconductor are used to mount the chip when flip-chip methods are used, and the terminals are along one side of the chip when the chips are vertically mounted. These methods increase the density of components that may be placed in a single package, but do not necessary deal with substrate contact, heat transfer, and other problems.
From the foregoing it may be seen that a need exists for an innovative system integration, or packaging technique to complement the corresponding advances in the miniaturization of device technology. There is an associated need for new packaging apparatus and techniques for integrating together multiple integrated circuit chips in a three dimensional manner so as to provide a highly efficient, economical and compact arrangement, while yet providing adequate thermal dissipation required for densely packed electrical circuits.